The present invention is generally related to a flat-panel display interfaces. In particular, the present invention is related to a high-speed flat panel display interface that processes RGB or YUV signals. More particularly, the high-speed flat-panel display interface includes offset and gain adjustments that are outside of the signal path such that high-speed operation is enhanced.
Display technologies are commonly available at lower costs due to mass markets such as personal computers (PCs). Displays are commonly available in a two types, namely, cathode ray tube type displays (CRTs) and flat-panel displays. Flat-panel displays include various technologies such as liquid crystal displays (LCDs), and TFT displays. CRT type displays are usually controlled by analog signals, while flat-panel displays can only process digital signals.
Many PC-based video graphics interfaces are configured to provide interface signals that are organized according to graphic color planes such as red, green, and blue (RGB). For example, a typical video graphics interface provides analog graphics signals for the red (R), green (G), and blue (B) color planes, as well as control signals for horizontal (HYSNC) and vertical timings (VSYNC). Since flat-panel displays require digital control signals, the analog graphics signals must be reformatted by an acquisition interface. The acquisition interface samples the RGB signals at a rate that is matched to a pixel clock rate of the video graphics interface. The sampled RGB signals are converted into digital signals, and provided to the flat-panel display at a clock rate that is appropriate for the flat-panel display.
According to one example, an apparatus that is arranged in accordance with the present invention includes a first programmable current source, a second programmable current source, a third programmable current sources, a first resistor, a second resistor, a first buffer, a second buffer, a third buffer, and an analog-to-digital converter. The first programmable current source is arranged to provide a gain current (IGAIN). The second programmable current source is arranged to provide an offset current (IOS). The third programmable current source is arranged to provide another offset current that is matched to the offset current (IOS). The first resistor is arranged to receive the gain current (IGAIN) and the offset current (IOS) to provide a first reference signal (VPOS). The second resistor is arranged to receive the other offset current (IOS) to provide a second reference signal (VNEG). The first buffer is arranged to provide a first buffered reference signal (VPOS2) in response to the first reference signal (VPOS). The second buffer is arranged to provide a second buffered reference signal (VNEG2) in response to the second reference signal (VNEG). The third buffer that is arranged to provide a buffered input signal (VX2) in response to an input signal (VX), wherein the third buffer is in an open loop configuration. The analog-to-digital converter is configured to receive the buffered input signal, the first buffered reference signal (VPOS2), and the second buffered reference signal (VNEG2). The analog-to-digital converter is also configured to provide a digital output signal (DOUT) in response to the buffered input signal (VX2). The analog-to-digital converter includes a gain setting that is changed by adjusting the first programmable current source, and an offset setting that is changed by adjusting the second and third programmable current sources.
According to another example, an apparatus that is arranged in accordance with the present invention includes a first current source, a gain DAC, an offset DAC, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, a fourth current mirror circuit, a first resistor, a second resistor, and an analog-to-digital converter. The first current source is arranged to provide a full-scale gain current (IGFS). The gain DAC is arranged to provide a gain current (IGAIN) by scaling the full-scale gain current (IGFS) in response to a gain setting (GAIN). The first current mirror circuit is arranged to provide a full-scale offset current (IOSFS) in response to a first current, wherein the first current includes the gain current (IGAIN) such that the full-scale offset current (IOSFS) is related to the gain current (IGAIN). The second current mirror circuit is arranged to provide a second current in response to the first current such that the second current is related to the gain current (IGAIN). The offset DAC is arranged to provide an offset current (IOS) by scaling the full-scale offset current (IOSFS) in response to an offset setting (OFS). The third current mirror circuit is arranged to provide a third current in response to the offset current (IOS) such that the third current is related to the offset current (IOS). The first resistor (R1) is arranged to provide a first reference signal (VPOS) in response to the second and third currents. The fourth current mirror circuit is arranged to provide a fourth current in response to the offset current (IOS) such that the fourth current is related to the offset current (IOS). The second resistor (R2) is arranged to provide a second reference signal (VNEG) in response to the fourth current. The analog-to-digital converter is responsive to an input signal (VX2), the first reference signal (VPOS) and the second reference signal (VNEG). The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the input signal (VX2). The analog-to-digital converter has an associated gain characteristic that is adjusted with the gain setting (GAIN), and an associated offset characteristic that is changed by adjusting the offset setting (OFS).